Securing theAutonomousInterplanetary Future
We are assembling a world-class engineering team to solve hard problems in aerospace. Select roles available for qualified U.S. persons.
Engineering Opportunities
We design radiation-tolerant silicon, optical links, and autonomous coordination software for spacecraft operating across Earth, lunar, and Mars orbits. Certain positions involve export-controlled technology and are limited to U.S. persons. All candidates subject to background verification.
Own RTL for our radiation-tolerant edge processor: deterministic timing logic, redundant datapaths, and hardware-accelerated orbital math for nodes operating in Earth, lunar, and Mars orbits.
- —Architect and implement synthesizable RTL for triple-modular-redundant (TMR) logic and majority-voting structures
- —Design deterministic, low-jitter timing paths for physical-layer time-of-flight measurement
- —Define microarchitecture for on-chip coprocessors (numerical propagation, cryptographic primitives)
- —Drive area, power, and timing closure in partnership with physical design and verification
- —Participate in tape-out readiness reviews and post-silicon bring-up
- —M.S. or Ph.D. in EE / Computer Engineering, or 8+ years of digital ASIC design
- —Expert Verilog / SystemVerilog; at least one full tape-out on a production process
- —Hands-on radiation-hardened-by-design (RHBD) or TMR / SEU-mitigation experience
- —Familiarity with commercial or open-source RTL-to-GDSII flows
- —U.S. person status required (work involves export-controlled technical data)
- —SOI, BiCMOS, or wide-bandgap (GaN) process exposure
- —Prior space, defense, or high-reliability silicon programs
Build the verification environment that proves our silicon behaves identically under nominal, adversarial, and radiation-induced fault conditions before we commit to a mask set.
- —Develop constrained-random and directed testbenches for TMR datapaths and timing-critical blocks
- —Model single-event upsets and fault injection to validate voter and recovery logic
- —Build picosecond-resolution jitter and skew sweeps for the physical-layer timing window
- —Own coverage closure, regression infrastructure, and sign-off criteria
- —Cross-check RTL against post-layout gate-level and parasitic-extracted simulations
- —B.S. or M.S. EE / CE with 5+ years of ASIC or FPGA verification
- —SystemVerilog / UVM or Python-based co-simulation frameworks (e.g. cocotb)
- —Experience with Verilator, Icarus, or commercial simulators; gate-level simulation
- —Strong scripting (Python) and CI discipline
- —U.S. person status required (work involves export-controlled technical data)
- —Formal verification
- —Fault-injection or safety-critical (DO-254, ISO 26262) backgrounds
Take our netlist from synthesis to a manufacturable GDSII, with layout rules that keep redundant logic physically separated and clock trees tight across every voting domain.
- —Run and tune synthesis, floorplanning, placement, CTS, and routing flows
- —Enforce spatial separation of redundant registers to prevent multi-node upsets
- —Own DRC, LVS, antenna, and parasitic-extraction sign-off
- —Characterize timing and power on extracted netlists with SPICE-level simulation
- —Manage tape-out packages, foundry shuttle logistics, and multi-project-wafer submissions
- —B.S. or M.S. EE with 5+ years of digital physical design
- —Proficiency with OpenROAD / OpenLane / Magic / KLayout or the commercial equivalents
- —Deep understanding of standard-cell libraries, PDKs, and layout-dependent effects
- —Comfortable with Tcl, Python, and Linux-based flow automation
- —U.S. person status required (work involves export-controlled technical data)
- —Radiation-hardened standard-cell libraries
- —Mixed-signal floorplanning
Design the analog and mixed-signal front-end that turns an incoming optical pulse into a clean, sub-nanosecond timestamp on-chip.
- —Design photodetector receive chains, comparators, and time-to-digital converters
- —Develop low-jitter clock generation and distribution (PLL / DLL) for the timing core
- —Perform noise, jitter, and radiation-sensitivity analysis on analog blocks
- —Characterize silicon on the bench and correlate against simulation
- —M.S. or Ph.D. EE with 6+ years of analog / mixed-signal IC design
- —Track record with TDCs, PLLs, or high-speed SerDes front-ends
- —SPICE-level simulation, layout supervision, and post-silicon lab work
- —U.S. person status required (work involves export-controlled technical data)
- —Optical receiver design
- —Cryogenic or rad-hard analog experience
Define how our hardware survives multi-year exposure across LEO, cislunar, and interplanetary environments, and prove it with test data.
- —Model mission radiation environments (TID, SEE, displacement damage) per orbit regime
- —Plan and execute heavy-ion, proton, and gamma test campaigns at accelerator facilities
- —Set derating, shielding, and mitigation requirements for silicon and board-level designs
- —Own reliability analyses (FMEA, worst-case, lifetime) and qualification documentation
- —M.S. or Ph.D. in Physics, Nuclear Engineering, or EE
- —5+ years of radiation effects testing and analysis for spaceflight electronics
- —Working knowledge of SPENVIS / OMERE / CREME-type environment tools
- —U.S. person status required (work involves export-controlled technical data)
- —NASA / DoD parts qualification standards
- —Beam-time scheduling experience
Stand up hardware-in-the-loop emulation of our silicon so protocol, timing, and autonomy teams can test against real logic long before tape-out.
- —Port ASIC RTL to rad-tolerant FPGA targets and build emulation platforms
- —Design evaluation boards and test fixtures for silicon bring-up
- —Build optical-loopback and timing-injection test rigs with the photonics team
- —Support flight software integration on emulated hardware
- —B.S. or M.S. EE / CE with 4+ years of FPGA development
- —Xilinx / Microchip toolchains; high-speed board design and signal integrity
- —Comfortable with oscilloscopes, TDR, and lab automation
- —U.S. person status required (work involves export-controlled technical data)
Design the laser terminals and link architecture for a persistent optical mesh spanning Earth orbit, lunar space, and Mars transit corridors.
- —Own end-to-end link budgets across LEO, cislunar, and interplanetary ranges
- —Specify transmitters, receivers, modulation formats, and pointing-acquisition-tracking systems
- —Design for autonomous blind-pointing acquisition from predicted ephemerides
- —Define optical requirements that feed the silicon timing front-end
- —M.S. or Ph.D. in Optical Engineering, Photonics, or Physics
- —5+ years with FSO, lasercom, or high-power laser systems
- —Pointing, acquisition, and tracking (PAT) system design
- —U.S. person status required (work involves export-controlled technical data)
- —Deep-space optical comm heritage
- —Photon-counting detectors
Build the distributed sensing payloads that let a cluster of spacecraft detect centimeter-scale, non-cooperative debris that ground radar cannot see.
- —Design multistatic lidar transmit / receive architectures across multiple platforms
- —Model photon scattering, detection sensitivity, and false-alarm rates
- —Develop star-tracker-based occultation detection requirements
- —Define calibration and cross-platform synchronization approaches
- —M.S. or Ph.D. in Optics, EE, or Physics
- —5+ years of lidar, remote sensing, or space-based sensor design
- —Radiometric modeling and detector characterization
- —U.S. person status required (work involves export-controlled technical data)
Build the high-fidelity propagation and conjunction-assessment models that run at the edge across geocentric, selenocentric, areocentric, and heliocentric frames.
- —Implement N-body propagation with gravitational harmonics, drag, and solar radiation pressure
- —Develop conjunction assessment, covariance propagation, and maneuver-planning algorithms
- —Design coordinate and time-scale transformations across planetary reference frames
- —Reduce algorithms to fixed-point or hardware-friendly forms with the silicon team
- —Ph.D. in Astrodynamics, Aerospace Engineering, or Celestial Mechanics (or M.S. + 8 years)
- —C++ or Rust for real-time systems; Python for analysis
- —Numerical integration, perturbation theory, and orbit determination
- —U.S. person status required (work involves export-controlled technical data)
- —Cislunar or interplanetary mission design
- —GMAT / Orekit / SPICE toolkits
Own the time-scale and relativistic corrections that keep nanosecond-level synchronization valid for nodes moving at orbital velocities through varying gravitational potentials.
- —Implement IAU-standard transformations between barycentric, geocentric, areocentric, and terrestrial time scales
- —Model clock drift, gravitational redshift, and velocity dilation for onboard oscillators
- —Define synchronization protocols and error budgets for time-of-flight ranging
- —Validate models against published ephemerides and ground-truth ranging data
- —Ph.D. in Physics, Geodesy, or Astronomy with focus on relativistic time / reference frames
- —Working knowledge of IERS conventions and planetary ephemeris products
- —Scientific computing in Python, C++, or Julia
- —U.S. person status required (work involves export-controlled technical data)
Fuse lidar, star-tracker, and telemetry data into confident debris tracks on power- and radiation-constrained hardware.
- —Develop multi-object tracking and data-association pipelines across distributed observers
- —Design neural and classical detectors for low-albedo targets against stellar backgrounds
- —Quantize and compress models for deployment on onboard accelerators
- —Define consensus thresholds for multi-node detection confirmation
- —M.S. or Ph.D. in ML, CV, Robotics, or Estimation; or 6+ years of experience
- —PyTorch or JAX; model quantization and hardware-aware optimization
- —Kalman / particle filtering, multi-hypothesis tracking
- —U.S. person status required (work involves export-controlled technical data)
Design the negotiation and planning logic that lets spacecraft resolve close approaches days in advance, with a human operator always able to override.
- —Build priority-based right-of-way negotiation and collision-avoidance planners
- —Verify proposed maneuvers against shared state to prevent secondary conjunctions
- —Design human-in-the-loop authorization flows and safe-mode fallbacks
- —Model game-theoretic behavior across cooperative and non-cooperative actors
- —M.S. or Ph.D. in Aerospace, Robotics, or Controls
- —Trajectory optimization and multi-agent planning
- —Experience shipping safety-critical decision logic
- —U.S. person status required (work involves export-controlled technical data)
Write the software that runs on our onboard nodes: deterministic, fault-tolerant, and able to operate for years without a ground-in-the-loop.
- —Develop real-time embedded software for rad-tolerant processors and custom silicon
- —Implement fault detection, isolation, and recovery (FDIR) and safe-mode logic
- —Integrate with GN&C, sensing, and communications subsystems
- —Build hardware-in-the-loop test infrastructure with the FPGA team
- —B.S. or M.S. CS / CE / EE with 5+ years of embedded or flight software
- —C, C++, or Rust on RTOS or bare metal; memory-safe practices
- —Experience with cFS, F Prime, or comparable flight frameworks
- —U.S. person status required (work involves export-controlled technical data)
Build the open-source routing and addressing stack that treats a spacecraft's trajectory as its network address and moves data across store-carry-forward links between planets.
- —Implement Bundle Protocol v7 (RFC 9171) and DTN convergence layers
- —Design kinematic addressing that adapts across gravitational reference frames
- —Develop predictive routing using ephemeris-driven contact plans
- —Maintain CCSDS and HDTN interoperability; contribute to open standards
- —M.S. CS or equivalent; 5+ years of networking or protocol development
- —Rust or C++; strong protocol design and specification skills
- —Familiarity with DTN, CCSDS, or space networking stacks (ION, HDTN)
- —International candidates welcome; open-source contributions encouraged
Build the consensus and ledger layer that records verified debris tracks and settles maneuver compensation between operators.
- —Design Byzantine-tolerant consensus for witness-threshold event confirmation
- —Implement the shared ledger for signed track assets and mutual-insurance settlement
- —Build the Zero-Trust API that lets international operators participate without core disclosure
- —Own observability, testing, and simulation of large node counts
- —M.S. CS or equivalent; 5+ years of production distributed systems
- —Expert-level Rust or Go
- —Consensus protocols, smart-contract platforms, or distributed ledgers
- —International candidates welcome
Design the challenge-response, signing, and key-management schemes that bind a node's identity to its physical location and survive decades in orbit.
- —Design physical-layer challenge-response protocols with hardware-enforced timing
- —Specify hardware cryptographic primitives with the silicon team
- —Own key hierarchy, provisioning, and long-lived key rotation for space assets
- —Threat-model spoofing, relay, and replay attacks on the mesh
- —M.S. or Ph.D. in Cryptography or Security, or 6+ years of applied crypto
- —Protocol design and formal analysis; post-quantum awareness
- —Hardware security modules or secure-element experience
- —U.S. person status required (work involves export-controlled technical data)
Build the high-fidelity simulation environment where thousands of virtual nodes, debris objects, and optical links are exercised before anything flies.
- —Develop scalable orbital, link, and network simulators with space-weather inputs
- —Support Monte Carlo campaigns for conjunction, detection, and consensus studies
- —Build visualization and analysis tooling for engineering and proposal teams
- —B.S. or M.S. in CS, Aerospace, or Physics with 4+ years of simulation work
- —C++ / Rust / Python; distributed compute and data pipelines
- —Familiarity with astrodynamics libraries and scenario tooling
- —International candidates welcome
Hold the full-stack picture from silicon to constellation and turn it into requirements, interfaces, and a mission roadmap across Earth, lunar, and Mars regimes.
- —Own system architecture, requirements flow-down, and interface control documents
- —Lead trade studies across orbit selection, node placement, and payload sizing
- —Run FMEA, risk management, and design reviews (SRR through CDR)
- —Support federal proposal technical volumes
- —M.S. or Ph.D. in Aerospace / Systems Engineering, or 12+ years of experience
- —End-to-end spacecraft or payload development through launch
- —SEMP, ICD, FMEA, and MBSE (SysML) fluency
- —U.S. person status required (work involves export-controlled technical data)
Take our hardware from bench to flight-ready: environmental qualification, integration with host spacecraft, and launch campaign support.
- —Plan and execute thermal-vacuum, vibration, and EMI/EMC qualification
- —Integrate payloads with host buses and rideshare providers
- —Develop test procedures, GSE, and anomaly resolution processes
- —B.S. or M.S. in Mechanical, Electrical, or Aerospace Engineering
- —5+ years of spacecraft or payload AI&T
- —Familiarity with GEVS / SMC-S-016 class environmental standards
- —U.S. person status required (work involves export-controlled technical data)
Run our non-dilutive funding pipeline across NASA, NSF, and DoD SBIR/STTR programs, and manage awarded contracts to milestone.
- —Own capture, proposal writing, and submission for SBIR / STTR and BAA opportunities
- —Coordinate technical volumes with engineering leads
- —Manage awarded contracts: reporting, deliverables, and transition planning
- —Track solicitations and build relationships with program offices
- —5+ years of federal proposal management with a record of SBIR / STTR awards
- —Working technical literacy in space systems or hardware
- —Excellent writing and program coordination
- —U.S. work authorization required